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NTD4302 Power MOSFET 68 Amps, 30 Volts
N-Channel DPAK
Features
* * * * * * *
Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS Specified at Elevated Temperature DPAK Mounting Information Provided
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V(BR)DSS 30 V RDS(on) TYP 7.8 mW @ 10 V ID MAX 68 A
N-Channel D
Applications
* DC-DC Converters * Low Voltage Motor Control * Power Management in Portable and Battery Powered Products:
i.e., Computers, Printers, Cellular and Cordless Telephones, and PCMCIA Cards
G S 4 4 12 3 CASE 369AA DPAK (Surface Mount) STYLE 2 1 3 CASE 369D DPAK (Straight Lead) STYLE 2 2
MARKING DIAGRAM & PIN ASSIGNMENTS
4 Drain YWW T 4302 4 Drain YWW T 4302 3 Source 1 Gate 2 Drain 3 Source Package DPAK DPAK Straight Lead DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel Publication Order Number: NTD4302/D
1 Gate
2 Drain
T4302 Y WW
= Device Code = Year = Work Week
ORDERING INFORMATION
Device NTD4302 NTD4302-1 NTD4302T4
(c) Semiconductor Components Industries, LLC, 2003
1
October, 2003 - Rev. 5
NTD4302
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Thermal Resistance - Junction-to-Case Total Power Dissipation @ TC = 25C Continuous Drain Current @ TC = 25C (Note 4) Continuous Drain Current @ TC = 100C Thermal Resistance - Junction-to-Ambient (Note 2) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 3) Thermal Resistance - Junction-to-Ambient (Note 1) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 3) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting T J = 25C (VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 17 Apk, L = 5.0 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 1. 2. 3. 4. When surface mounted to an FR4 board using the minimum recommended pad size. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%. Current Limited by Internal Lead Wires. Symbol VDSS VGS RJC PD ID ID RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg EAS TL Value 30 20 1.65 75 68 43 67 1.87 11.3 7.1 36 120 1.04 8.4 5.3 28 -55 to 150 722 260 Unit Vdc Vdc C/W Watts Amps Amps C/W Watts Amps Amps Amps C/W Watts Amps Amps Amps C mJ C
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NTD4302
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 A) Positive Temperature Coefficient Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 30 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 30 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Negative Temperature Coefficient Static Drain-Source On-State Resistance (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 6) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Ga e C a ge Gate Charge (VDS = 24 Vdc, ID = 2.0 Adc, Vd 2 0 Ad VGS = 10 Vdc) BODY-DRAIN DIODE RATINGS (Note 5) Diode Forward On-Voltage (IS = 2.3 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc) (IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time e e se eco e y e (IS = 2.3 Adc, VGS = 0 Vdc, 2 3 Ad Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Indicates Pulse Test: Pulse Width = 300 sec max, Duty Cycle 2%. 6. Switching characteristics are independent of operating junction temperature. VSD - - - trr ta tb Qrr - - - - 0.75 0.90 0.65 39 20 19 0.043 1.0 - - 65 - - - C ns s Vdc (VDD = 24 Vdc, ID = 20 Adc, VGS = 10 Vdc, Vdc RG = 2.5 ) (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc, Vdc RG = 2.5 ) (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc, Vdc RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf td(on) tr td(off) tf QT Qgs (Q1) Qgd (Q2) - - - - - - - - - - - - - - - 11 15 85 55 11 13 55 40 15 25 40 58 55 5.5 15 20 25 130 90 20 20 90 75 - - - - 80 - - nC ns ns ns (VDS = 24 Vdc, VGS = 0 Vdc, Vd Vd 1.0 f = 1 0 MHz) Ciss Coss Crss - - - 2050 640 225 2400 800 310 pF VGS(th) 1.0 - RDS(on) - - - gFS - 0.0078 0.0078 0.010 20 0.010 0.010 0.013 - Mhos 1.9 -3.8 3.0 - Vdc V(BR)DSS 30 - IDSS - - IGSS - - - - 1.0 10 100 nAdc - 25 - - Vdc mV/C Adc Symbol Min Typ Max Unit
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NTD4302
50 ID, DRAIN CURRENT (AMPS) 60 VDS > = 10 V ID, DRAIN CURRENT (AMPS) 50 40 30 20 10 0 TJ = 25C TJ = 100C TJ = -55C
VGS = 4 V
TJ = 25C VGS = 3.8 V
40
VGS = 4.4 V VGS = 4.6 V VGS = 5 V VGS = 7 V VGS = 10 V
30
20
VGS = 3.4 V VGS = 3.2 V VGS = 3.0 V
10 0 0 0.5 1
VGS = 2.8 V
1.5
2
2.5
3
2
3
4
5
6
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE ()
0.1
RDS(on), DRAIN-TO-SOURCE RESISTANCE ()
ID = 10 A TJ = 25C
0.015
TJ = 25C
0.075
VGS = 4.5 V 0.01
0.05
VGS = 10 V 0.005
0.025
0 0 2 4 6 8 10 VGS, GATE-TO-SOURCE VOLTAGE (V)
0.00E+00
0
1.00E+01
2.00E+01
3.00E+01
4.00E+01
5.00E+01
6.00E+01
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance vs. Gate-To-Source Voltage
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.6 ID = 18.5 A VGS = 10 V 10000
Figure 4. On-Resistance vs. Drain Current and Gate Voltage
VGS = 0 V TJ = 150C
1.4
1.2
IDSS, LEAKAGE (nA)
1000
100 TJ = 100C 10
1
0.8 0.6 -50
1 -25 0 25 50 75 100 125 150 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current vs. Voltage
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NTD4302
6000 VDS = 0 V 5000 C, CAPACITANCE (pF) Ciss 4000 3000 2000 Crss VGS 0 VDS Coss VGS = 0 V TJ = 25C 12.5 QT VD 30 VDS, DRAIN-TO-SOURCE- VOLTAGE (V) 1 VGS, GATE-TO-SOURCE- VOLTAGE (V)
10
25
7.5 VGS 5 Q1 Q2
20
Crss
Ciss
15
1000 0 10
2.5 ID = 2 A TJ = 25C 0 10 20 30 40 50 Qg, TOTAL GATE CHARGE (nC)
10
10
20
30
0
0 60
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge
1000 IS, SOURCE CURRENT (AMPS) VDD = 24 V ID = 18.5 A VGS = 10 V t, TIME (ns)
25
VGS = 0 V TJ = 25C
20
15
100 tf td(off) tr td(on) 10 1 10 RG, GATE RESISTANCE () 100
10
5
0 0.5
0.6
0.7
0.8
0.9
VSD, SOURCE-TO-DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
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NTD4302
100 ID , DRAIN CURRENT (AMPS) 100 ms di/dt VGS = 10 V SINGLE PULSE TC = 25C 1 ms IS trr ta 10 ms dc tp IS 10 100 0.25 IS tb TIME
10
RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.1 1
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Diode Reverse Recovery Waveform
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE DUTY CYCLE 100 D = 0.5 0.2 0.1 0.05 0.02 0.01
MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT
10
1
P(pk) t2 DUTY CYCLE, D = t1/t2 1E-03 1E-02 1E-01 t, TIME (seconds) 1E+00 t1
0.1 SINGLE PULSE 0.01 1E-05 1E-04
RJA(t) = r(t) RJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TA = P(pk) RJA(t) 1E+02 1E+03
1E+01
Figure 13. Thermal Response - Various Duty Cycles
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NTD4302 INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
6.20 0.244
interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
3.0 0.118
2.58 0.101
5.80 0.228
1.6 0.063
6.172 0.243
SCALE 3:1
mm inches
SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 14 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.
Figure 14. Typical Stencil for DPAK and D2PAK Packages
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.
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CCCCC C CCC C CC CCCCC CCC CC CCCCC C
CC CC CC CC CC
SOLDER PASTE OPENINGS
STENCIL
NTD4302
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 -189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
STEP 1 PREHEAT ZONE 1 "RAMP" 200C
STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP"
STEP 4 HEATING ZONES 3 & 6 "SOAK"
DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C
160C
STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT
150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C
SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 15. Typical Solder Heating Profile
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NTD4302
PACKAGE DIMENSIONS
DPAK CASE 369AA-01 ISSUE O
-T- B V R
4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.033 0.045 0.018 0.023 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.88 0.46 0.61 0.83 1.14 0.46 0.58 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 ---
C E
A S
1 2 3
Z U
F L D
2 PL
J
DIM A B C D E F J L R S U V Z
0.13 (0.005)
M
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
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NTD4302
PACKAGE DIMENSIONS
DPAK CASE 369D-01 ISSUE O
B V R
4
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ---
Z A
3
S -T-
SEATING PLANE
1
2
K
F D G
3 PL
J H 0.13 (0.005)
M
DIM A B C D E F G H J K R S V Z
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTD4302/D

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